Electronic mathematics trainer

ABSTRACT

The specification discloses an electronic mathematics trainer including a problem sheet bearing a plurality of arithmetic problems. An arithmetic problem display holder receives the problem sheet and includes lamps therein for sequentially being illuminated to indicate sequential ones of the arithmetic problems to be solved. A keyboard encoder enables a student to manually enter the arithmetic problem presently illuminated on the problem sheet. A display unit displays the arithmetic problem which is entered into the encoder. Circuitry is provided to compute the correct answer to the arithmetic problem entered into the encoder, along with at least one incorrect answer. The incorrect and correct answers are displayed on the display unit. Structure is provided to enable the selection of one of the displayed answers. If the correct answer is selected, the answer to the problem is then displayed adjacent the displayed problem. Circuitry in the display holder is responsive to the selection of the correct displayed answer in oder to advance the illumination of the lamps to the next arithmetic problem on the problem sheet. Selection of the correct displayed answer also clears the arithmetic problem displayed on the display unit.

FIELD OF THE INVENTION

This invention relates to training devices, and more particularlyrelates to a device and technique for teaching arithmetic skills.

THE PRIOR ART

A variety of different types of systems have been heretofore developedfor teaching mathematical and arithmetic skills to students and thelike. Many of the previously developed systems have required the teacherto input a desired arithmetic problem which must be solved by aplurality of students. Such systems have not then enabled students towork the problems at their own rate in accordance with their individualskills. Moreover, such previously developed systems have not attemptedto reinforce the skills being learned by requiring the students to inputthe problem being solved. Prior mathematic teaching systems have alsonot been completely satisfactory in reinforcing the correct solution tothe problem to the student, and have not provided sufficient reward to astudent for the correct and speedy solution of a particular problem.

SUMMARY OF THE INVENTION

In accordance with the present invention, an electronic mathematicstraining device is provided which substantially eliminates or reducesthe problems and disadvantages heretofore associated with previouslydeveloped mathematics teaching techniques.

In accordance with the present invention, an electronic mathematicstrainer includes structure for selectively entering an arithmeticproblem to be solved. Circuitry computes the correct answer to thearithmetic problem, in conjunction with at least one incorrect answer tothe arithmetic problem. The correct and incorrect answers are displayed.Structure is operable to select one of the displayed answers. Circuitryclears the entered arithmetic problem only upon the selection of thecorrect displayed answer.

In accordance with another aspect of the invention, an electronicmathematics trainer includes a problem sheet bearing a plurality ofarithmetic problems. A display holder is adapted to receive the problemsheet, and contains structure for sequentially indicating ones of thearithmetic problems on the problem sheet to be solved. A keyboardencoder enables the entry of the arithmetic problem indicated on thedisplay holder. A display unit displays the arithmetic problem enteredinto the encoder. Circuitry computes the correct answer to thearithmetic problem entered by the keyboard encoder, along with anincorrect answer to the arithmetic problem. The correct and incorrectanswers are displayed on the display unit. Circuitry is operable forselecting one of the displayed answers. Circuitry in the display holderis responsive to the selection of the correct displayed answer foradvancing the indication of the problem to be solved to the nextarithmetic problem on the problem sheet. Circuitry clears the arithmeticproblem displayed by the display unit upon selection of the correctdisplayed answer.

In accordance with yet another aspect of the invention, a problem sheetholder is provided for use with a sheet bearing a plurality ofarithmetic problems in an electronic mathematics trainer. A base portionreceives the sheet containing a plurality of arithmetic problems.Structure is provided to sequentially indicate each problem on theproblem sheet. Stucture is provided for retaining the problem sheetwithin the base portion until all problems on the problem sheet havebeen indicated.

In accordance with yet another aspect of the invention, a method ofteaching arithmetic skills includes displaying a plurality of arithmeticproblems to be solved. Decimal numbers and the arithmetic operation ofone of the arithmetic problems are then entered into an electronicmathematics trainer. The entered arithmetic problem is displayed to astudent without an answer. The correct answer and at least one incorrectanswer are computed and displayed. The student selects one of theanswers. The correct answer is then displayed on the entered problemupon the selection of the correct answer.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and furtherobjects and advantages thereof, reference is now made to the followingdescription taken in conjunction with the following drawings:

FIG. 1 is a front view of the preferred system of the electronicmathematics trainer, including a keyboard encoder and a problem sheetholder;

FIG. 2 is an open side view of a problem sheet holder of the preferredsystem of the invention;

FIG. 3 is a detailed view of the problem display unit appearing on thefront of the keyboard encoder;

FIG. 4 is a block diagram of the electronic circuitry of the preferredsystem of the invention;

FIG. 5 is a schematic diagram of the keyboard encoder of the preferredsystem;

FIG. 6 is a schematic diagram of the input storage register and controlof the invention;

FIG. 7 is a schematic diagram of the arithmetic logic unit of theinvention;

FIG. 8 is a schematic diagram of the display multiplexers and drivers ofthe invention;

FIG. 9 is a schematic diagram of the random answer generator of theinvention;

FIG. 10 is a schematic diagram of the answer position and selectioncontrols of the invention;

FIG. 11 is a schematic diagram of the display selector of the invention;

FIG. 12 is a schematic diagram of the problem sheet holder of thepreferred system; and

FIG. 13 is a schematic diagram of the automatic random problem controlof the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates the two basic components which comprise the preferredsystem 20 of the invention. The two basic components include a problemsheet holder 22 electrically connected by a wire 24 to a keyboardencoder and display 26.

The holder 22 comprises a rectangular housing with a slot formed betweenan aluminum frame 28 and a plexiglass face plate 30 wherein atranslucent or transparent plastic arithmetic problem sheet 32 isinserted. Insertion of the problem sheet 32 trips a locking switch 34,causing a solenoid locking pin 36 to secure the sheet 32 within theholder 22 until a student has successfully answered all the problems.

A plurality of problem lamps 38 are located directly below the faceplate 30 in an array of ten rows of ten columns. A problem lamp 38 inthe first row of the first column is initially lit to display the firstproblem on sheet 32. Each time the student selects a correct answer onthe keyboard 26, the holder 22 displays the next problem by lighting anext lamp 38 in the array.

The keyboard 26 has a plurality of problem number keys 40 and arithmeticoperation keys 42 for encoding the problem displayed on holder 22. Thenumber keys 40 consist of ten pushbuttons for each of the numbers fromzero through nine. The arithmetic operation keys 42 consist of fourpushbuttons, representing the arithmetic operations of addition,substraction, mulitplication, and division. An operation mode indicator44 can be selectively positioned above the operation key 42 as aremainder to the student of the type of operation being performed.

A problem display window 46 is located on the face of keyboard 26 andincludes seven segment light emitting diodes (LEDs) to display theproblem as it is encoded by the student. The decimal digits of thecorrect answer will be electronically displayed in the proper locationin the window display 46 when the student has successfully completedeach problem.

A student's entry of a problem into the keyboard 26 enables theelectronic circuitry of the invention, as will be subsequently describedin detail, to calculate the solution to the problem and to randomlygenerate two incorrect answers. These three answers are visuallydisplayed to the student in the three windows of a solution display 48.A solution keyboard 50 is located directly below the display 48 on theface of the keyboard 26, so that each of the three pushbuttons andkeyboard 50 corresponds to an answer displayed in one of the threewindows of display 48.

A student's selection of an incorrect answer from the keyboard 50 willonly cause that answer displayed in that window of the solution display48 to be blanked out. When the student selects the correct answer fromthe keyboard 50, two things will happen: (1) the correct answer will bedisplayed in the proper place in display window 46; and (2) a studentactivated clear bar 52 can now be operated to erase the problem from thedisplay window 46, so the student may go on to enter the next problemfrom the holder 22.

An automatic random problem control switch 54 is located on the face ofkeyboard 26 along with the automatic operation mode selector 56. Placingswitch 54 in "ON" state eliminates manual control in entering arithmeticproblems into the trainer, as problems can now be automatically randomlygenerated. The operation mode selector 56 enables the student toautomatically set the operation mode of automatically randomly generatedproblems to addition, subtraction, multiplication, division, or randomlyselected mode.

FIG. 2 illustrates in greater detail the location of problem sheet 32 inthe holder 22. This view clearly shows the open space formed between thecover frame 28 and the face plate 30. The locking switch 34 and itsassociated pin 36 are located at the top of holder 22, so that the pin36 is inserted into a hole formed in sheet 32 when the locking switch 34is tripped.

In operation of the preferred system of the present electronicmathematics trainer, a problem sheet 32, containing an array ofmultiplication problems, is inserted into the slot formed on the holder22, thereby tripping switch 34 and locking the sheet 32 in place throughthe action of the locking pin 36. The problem sheet 32 is now securelylocated between the cover sheet 28 and the face plate 30, and the sheet32 will remain locked in holder 22 until the student has correctlyanswered all the problems.

Assume for this example, that the one problem lamp 38 that is litilluminates the multiplication problem 3 × 3. The student enters theproblem in keyboard 26 by the following steps: depressing the number 3button of numbered keys 40 for the multiplicand 3, depressing the × keyof the arithmetic operation keys 42, and finally by again depressing thenumber 3 key of number keys 40 for the multiplier 3. The operation modeindicator 44 should now be positioned over the multiplicaton symbol ofindicator 44, reminding the student of the arithmetic operation of thisproblem. The problem 3 × 3 should now be displayed in the problem window46.

The circuitry in keyboard 26 processes the correct answer 9, along withtwo randomly chosen incorrect answers, e.g., 6 and 8, and displays thesethree numbers as possible solutions in the solution display 48. Thesethree answers are shown in an illuminated digital display in each of thethree windows of the display 48. An important aspect of the invention isthat the correct answer is randomly displayed in different ones of thethree windows of display 48.

If the student selects the incorrect answer 6, by depressing the buttonunder this answer on keyboard 50, the machine automatically blanks outthis answer, but retains the unanswered problem in the display window46.

If the student now selects the correct answer by depressing the buttonon the solution keyboard 50 below the number 9 in a window of display48, then this correct answer will be displayed in its proper place inthe problem display window 46. The machine will also cause the signal tobe transmitted through the wire 24 to holder 22, causing the nextproblem lamp 38 in the array to be illuminated. The student may nowblank the problem 3 × 3 from the window 46 by depressing clear bar 52.The machine is now ready for the student to enter the next problem inthe same manner as that described above.

The student will advance through this problem solving process until theproblems on sheet 32 have been correctly answered, thereby releasing thelocking pin 36 for removal of the sheet 32. Upon removal of this problemsheet 32, the student's mathematics training may be continued byinsertion of another clear plastic problem sheet 32 into the machine.

In another embodiment of the invention, the keyboard encoder and displaymay be readily modified to enable a blind student to use the mathematicstrainer. The individual keys comprising the number keyboard 40 and theoperation keyboard 42 may bear the raised symbols of the Braillealphabet to designate the number of operation encoded by that key.Similarly, the clear bar 52 may have letters in the Braille alphabetembossed on the face of this key to designate its function in thepreferred system 20.

The problem display window 46 may include heated elements on the face ofkeyboard encoder and display 26, suitable for indicating the outline ofthe digits in the problem on the answer by touching the heated segmentsof these elements. The use of such heated elements in place of the sevensegment light emitting diodes in keyboard encoder and display 26 wouldraise the power requirements to operate this alternate embodimet of theinvention.

A blind student would operate the alternate embodiment of the inventionby initially inserting a problem sheet 32 encoded in Braille into theproblem sheet holder 22. As in the preferred system 20, the array ofproblem lamps 38 would sequentially light to indicate to the student thenext problem to be keyed into the keyboard encoder and display 26.However, a blind student would be able to detect the correct problem onproblem sheet 32 by sensing the heat generated by the subjacent lamp 38.Thus, the translucent plexiglass face plate 30 may be constructed ofanother material better suited for conducting the heat generated by theproblem lamps 38 when it is to be used with keyboard encoder and display26.

FIG. 3 is a detailed view of the problem display window 46 on thekeyboard encoder display 26 (FIG. 1).

The digital displays 130, 131, 132, 133, and 134 comprise the displayfor the decimal numbers of the arithmetic problem and its selectedcorrect answer. The displays 130-134 may comprise the familiar sevensegment light emitting diode displays. In an alternate embodiment of thetrainer for a sightless person, heat emitting elements comprisingfilament wire may replace the light emitting diodes.

The lamp displays 135 and 136 are both illuminated to indicate thedivision operation, wherein the digital displays 133 and 134 appear asthe dividend of the entered problem and digital display 132 appears asthe divisor. In the division operation mode the selected correct answerwould appear as digital display 131. The lamp display 136 is alsoilluminated in the addition, subtraction, and multiplication operationsto form the bar separating the problem from the answer.

The lamp displays 137, 138, and 139 are illuminated to indicate eitherthe addition (+), subtraction (-), or multiplication (×) operation signsfor the entered problem. The operation signs for these three arithmeticoperations appear by illuminating these lamp displays. The problem isdisplayed in digital displays 130 and 131 while the selected correctanswer appears in digital displays 133 and 134 below the lamp display136.

FIG. 4 illustrates the preferred system of the invention in blockdiagram form. The circuitry described in this diagram is mounted in thekeyboard encoder and display 26. A keyboard encoder circuit 60 detectsthe key depressing action of the student and converts the decimal oroperation keys, 40 and 42, into a binary coded digit needed foroperation of the machine. This circuit also provides a pulse signal toindicate that a key has been pressed and that data is available.

The data received from the keyboard encoder 60 is received by an inputstorage register and control circuit 62, which routes this data to aseries of storage registers. Here the information is maintained for useby both a display multiplexer and driver circuit 64 and an arithmeticunit 66. The information to be operated on is retained in theseregisters until a correct answer is selected by the student. Theregister retains the information of the operation mode selected to allowthat operation to continue and set the machine up for the next problem.

The arithmetic logic unti 66 processes the information stored in theregisters of unit 62 and processes it to derive an answer, if one ispossible. The unit 66 only accepts as a valid problem positive integaroperations. An invalid problem will cause unit 66 to reset, making itready for a valid problem. This unit 66 uses a method commonly known asserial decimal mathematics to carry out the operations of addition,subtraction, multiplication and division. Addition is accomplished byincrementing an output register as a companion register is decrementedto zero. Subtraction operates similarly, except both registers aredecremented. Multiplication is accomplished by successive addition, anddivision is executed by successive subtraction.

The display multiplexer and driver 64 selects the outputs from all thestorage registers in the machine and makes them available to the displaydecoder and drivers. In order to prevent confusion in the mind of thestudent, this process incidentally includes blanking and zero displaysuppression of undesired digits. The unit 66 further provides lampdrivers for the display of the operation mode on the keyboard encoderand display 26. The unit 64 also alerts the arithmetic logic unit 66 anda display selector unit 68 to specially set up for the divisionoperation.

A random answer generator unit 70 compares the true answers of theproblem computed by the unit 66 with randomly generated numbers to bepresented as alternate choices to the student. These numbers generatedin this fashion are stored in four registers for use by the displaymultiplexer and driver unit 64.

An answer position selection control unit 72 selects the order in whichthe correct answer and two incorrect answers are placed in solutiondisplay 48. A student selection of a correct answer enables the unit 72to instruct the display selector 68 to place the correct answer in theproper position in the problem display window 46. If the student selectsan incorrect answer, this unit 72 will blank out the incorrect answer inthe solution display 48.

A random problem control unit 74 may be switched on to generate randomproblems for automatic entry into the input storage unit 62 for solutionby the trainer. The control unit 74 enables the student to select theoperation mode for the automatically entered problems to bepredetermined as one of the four arithmetic operations or to be randomlygenerated arithmetic operation.

The display selector unit 68 enables the machine to select which one ofthe machine's eleven displays shall be energized to display theinformation placed on the display drive lines by the display multiplexerand driver unit 64. The format for displaying this information isgoverned by the operation selected by the student as well as thestudent's progress in solving a problem.

FIG. 5 illustrates a schematic diagram of the keyboard encoder 60 (FIG.4) that converts the student's action of depressing a decimal oroperation key into a binary type code utilized by the system 20. Thiscircuit also provides a pulse signal to the other circuits, indicatingthat data is now available.

A 16 position matrix 80 has 14 places in a rectangular array ofintersections of input and output leads that correspond to the 14pushbuttons on the faces of keyboard 26. As is indicated in the matrix80, these intersections correspond to the decimals zero through nine andthe symbols for the four arithmetic operations of division,multiplication, addition and subtraction.

At the same time a student depresses a decimal key 40 or an operationkey 42 shorting a point on the matrix 80, current is allowed to flowfrom a positive power terminal 81 through resistor 82, thereby enablingcapacitor 84 to charge and forward bias a PNP transistor 86. Thecollector of transistor 86 is connected through resistor 88 to theground lead 103. The base of transistor 90 is connected to both abiasing resistor 92 and a capacitor 94 which couple transistor 90 to thecollector of transistor 86. The capacitor 94 forces transistor 90 on fora short period of time, thereby providing a direct output pulse throughits collector to indicate that data is present.

A PNP transistor 96 has its emitter connected through the chargingcircuit of resistor 82 and capacitor 84 to the positive power terminal81, while its base is connected to the charging circuit through aresistor 98. The collector of transistor 96 is connected to resistor 100to the base of an NPN transistor 102, which has its emitter connected toa negative power terminal 103. The base of transistor 96 is furtherconnected to two vertical branches in the matrix 80. One of thesebranches is connected through diode 97 while the other branch isconnected directly to the base of the transistor 96. Thus, as differentpoints in the two branches are shorted, transistor 96 is forced intoconduction and is in turn forcing transistor 102 to conduct, therebychanging the output at the collector of transistor 102 from a logic highlevel to a low level.

Another PNP transistor 104 is similarly connected to two branches of thematrix 80 in order to cause the collector of an NPN transitor 106 toconduct, thereby changing its output from a high level to a low level.The transistor 104 also has its emitter connected to the chargingcircuit of resistor 82 and capacitor 84, and the base of transistor 104is connected with resistor 108 to the same circuit. The collector oftransistor 104 is connected through resistor 110 to the base of thetransistor 106, which has its emitter tied to a negative power source.The base of transistor 104 is connected to the center two verticalbranches of the matrix 80, one of these connections is made throughdiode 112, which has its cathode connected to both the cathode of diode102 and the second vertical branch of the matrix 80. Thus, as any of theeight points on these two branches are shorted, the transistor 104 isforced into conduction, thereby forcing the transistor 106 to conductand placing a logic low level output on its collector attached to pin 2.

The top horizontal lead in the matrix 80 is connected through resistor114 to the base of an NPN transistor 116. The second horizontal leadfrom the top is connected through diode 118 through the resistor 114 tothe base of transistor 116, having its emitter connected to a negativepower source. Thus, depressing any of the six keys corresponding todifferent points on the matrix 80 crossed by the two horizontal leadsforces the transistor 116 to conduct, placing a logic low level at itscollector terminal tied to the output pin 4.

Similarly, the second and third horizontal leads counting from the topof matrix 80, are connected to the base of an NPN transistor 120. Thesecond horizontal lead is connected through a diode 122 and a resistor124 to the base of transistor 120. The third horizontal lead isconnected directly through the resistor 124 to the base of transistor120, which has its emitter tied to negative terminal 103. The bottomhorizontal lead in the matrix 80 is connected through limiting resistor126 directly to the negative power source. Thus, a student's action ofdepressing any of the keys corresponding to the decimal associated withthe second and third horizontal leads to the matrix 80 causes thetransistor 120 to conduct, thereby placing a logic low level signal atits collector which is tied to the pin 8.

Table I is included below to show the binary coded information signalgenerated for each of the decimal and operation keys 40 and 42 that maybe activated by a student.

                  TABLE I                                                         ______________________________________                                        TABLE OF OUTPUTS                                                              ______________________________________                                        KEY           K       1       2     4     8                                   NONE          1       1       1     1     1                                   1             C       1       0     0     0                                   2             C       0       1     0     0                                   3             C       1       1     0     0                                   4             C       0       0     1     0                                   5             C       1       0     1     0                                   6             C       0       1     1     0                                   7             C       1       1     1     0                                   8             C       0       0     0     1                                   9             C       1       0     0     1                                   0             C       0       0     0     0                                   +             C       0       0     1     1                                   ×       C       1       0     1     1                                   -             C       0       1     1     1                                   ÷         C       1       1     1     1                                   ______________________________________                                    

FIG. 6 illustrates a schematic diagram of the input storage registersand control 62 (FIG. 4) that routes that data from the keyboard to astorage area, where it is maintained for later use by the display andmathematics systems of the preferred system 20. At the conclusion ofeach problem, all the information except the selected operation mode iscleared from each storage area for further problem solving. This allowsthe machine to set its displays up to continue the operation selectedwhen other problems are encoded by a student.

A total of four storage registers, 140, 142, 144 and 146, are includedto receive the binary coded signals generated by the student depressingdecimal and operation keys in the matrix 80 (described above). Storageregisters 140-146 may comprimise for example, Ser. No. 74195 storageregisters. The low going pulse signal placed on output pin k by theaction of depressing a key in the matrix 80 is inverted by an inverter148 and fed to each of the Ck leads of the storage resistors 140, 142,144 and 146. The "data present" signal is transmitted through diode 150to the Ck leads of storage registers 140 and 142. Similarly, diode 152and 154 transmit this signal to the Ck lead of storage registers 144 and146, respectively. This now enables the information present to be loadedinto one of the desired storage registers 140, 142, 144 and 146.

A reset pulse may be applied to the R terminal of storage registers 140,142 and 146 to clear all information previously stored in theseregisters. As described above, the operation mode selected, stored inregister 144, is retained to set the preferred system 20 of theinvention for the next operation. The reset pulse from pin R is alsoapplied to the R terminals of the control flip-flops 156 and 158,placing them in their starting positions. The starting position of thecontrol flip-flop 156 enables the storage register 142 to loadinformation as it becomes available by transmitting a signal from the Qoutput terminal of control flip-flop 156 through diode 160 to the Cklead of the register 142. Similarly, the starting position of thecontrol flip-flop 158 operates to prevent register 146 from loadinginformation by transmitting a signal from the Q output terminal offlip-flop 158 through the diode 162 to the Ck terminal of register 146.

Setting storage register 142 in its starting position enables binarycoded decimal digits to be placed in the register 142 through its inputterminals. Since the output terminals of register 142 are clocked inparallel to the input terminals of the register 140, the reception of asignal indicating a second successive binary coded decimal digit placesthis information in the storage register 142 and passes the firstinformation to the storage register 140. This process of passinginformation from storage register 142 to register 140 will continueuntil the binary coded information signal from the matrix 80 indicatesan operation mode is selected.

The selection of an operation mode is detected by diodes 164 and 166,enabling a signal to pass through the inverter 168 and transmitting asignal to the S terminal of the flip-flop 156 which disables registers140 and 142. This signal is also transmitted through the inverter 170through a diode 172 to the Ck lead of the operations storage register144. This allows the binary coded operation signal to be stored in theregister 144. The signal from inverter 170 is also transmitted to the Jterminal of flip-flop 158, enabling the storage register 146 to receivedata by setting on the falling edge of the information signal from thematrix 80.

The output signal from the storage register 146 is monitored by diodes174 and 176 to prevent an operation code from being entered in thisregister 146. If the diodes 174 and 176 detect a logic level indicatinga control code, a signal is transmitted through inverter 178 to the Sterminal of the flip-flop 158, resetting it to allow another binarycoded information signal to be received. This new or second control codeis now the operation mode stored in the operation storage register 144,thereby enabling the student to correct an erroneous entry. Upon entryof a BCD signal for a decimal digit into register 146, the output atterminal Q of the flip-flop 158 goes low, indicating on the KR pin thatall information necessary for the operation of the problem is nowpresent. The output of all four registers is made available to othercircuits of the preferred system of the invention.

FIG. 7 illustrates a schematic diagram of the arithmetic logic unit 66(FIG. 4) that takes the information stored in the input storageregisters and controls 62 (FIG. 4) and processes it to derive an answer,if one is possible.

A timer 200 has two of its input terminals, + and Rst, connecteddirectly to a positive voltage source, which source is also connectedthrough resistor 202 to the Tr terminal and through resistor 204 to theTh terminal of the timer 200. A "data is ready" signal is applied as alow level pulse to the Kr pin through capacitor 206 to the Tr terminalof the timer 200. The timer 200 is connected directly to ground throughits terminal G, while terminals Th and Fm are connected to groundthrough capacitors 208 and 210 respectively. A timer 200 could consistof an integrated circuit type NE 555.

A pulse generated at the output terminal 0 of the timer 200 is appliedthrough an inverter 212 to the following three components: Y inputterminal of a decimal decoder 214 and to a diode 215, the Ck terminal ofa control flip-flop 216, and the Tr terminal of a second timer 218through a capacitor 219. The location of each of the three circuitcomponents in relation to other elements of the circuit is describedbelow.

First, the decimal decoder 214 acts as a four-position switch to loadthe binary coded decimal digits placed at the input terminals P₀ -P₃ ofthe decade counters 220, 222, 224, and 226. The decade counters 220-226may consist of, for example, four TTL decade counters of the type 74192.The decade counter 220 is connected through diode 228 from an outputterminal of the decoder 214. A plurality of diodes 230 connect outputterminals of decoder 214 to the load terminal decade counter 222.Similarly, a plurality of diodes 232 and 234 connect output terminals ofdecoder 214 to the decade counters 224 and 226, respectively. Finally,the signal from the diode 215 is fed to the counter control circuitryoperating through an inverter 238, described below.

Secondly, the pulse generated at the output terminal of the timer 200 isapplied to the control flip-flop 216, thereby setting the output atterminal Q of the flip-flop 216. The control flip-flop 216 may consistof, for example, one-half of a TTL dual flip-flop of the type 7476. Theoutput from terminal Q of flip-flop 216 is applied through diode 236,inverter 238, and a second inverter 240 to a plurality of diodes 242,244, 246, and 248. Diodes 242 and 244 enable the flip-flop 216 to setdecade counter 224 through an inverter 250 to count up or through aninverter 252 to count down. Similarly, diodes 246 and 248 enableflip-flop 216 to set decade counter 222 through an inverter 254 to countup or through an inverter 256 to count down. A plurality of diodes 258feed a clock pulse KA to each of the inverters 250, 252, 254 and 256,described above.

Decade counters 222 and 224 also receive information as to the operationmode selected. Cl, the least significant digit in the binary code forthe operation selected, is applied through a diode 260 through aninverter 262 to a pair of diodes 264 connected to the inverters 250 and252 of decade counter 224. C2, the signal for the next least significantbinary digit in the operation mode selected, is applied through a diode266 to inverter 256 of decade counter 222. The same signal is appliedthrough an inverter 268 through diode 270 to the same inverter 256.There is one last information signal DD, generated by the displaymultiplexer and driver unit 64 (FIG. 4), which alerts the arithmeticlogic unit 66 to the selection of the division operation. The DD signalis applied through a diode 272 to the inverter 252 attached to the"count down" terminal of the decade counter 224. This same signal DD isalso applied through an inverter 274, through a diode 276, and then tothe inverter 250 attached to the "count up" terminal of the decadecounter 224.

Third and finally, the timer 218 has its + terminal attached directly toa positive voltage source, which also is connected to the Tr terminalthrough a resistor 278. The Th terminal and the Fm terminal of the timer218 are connected through their respective capacitors 280 and 282 to aground, which is also connected to the G terminal of timer 218.

A fifth decade counter 284, a control flip-flop 286 and the decadecounter 226 form the basic components of a counter circuit used by themachine in multiplication and division problems. The flip-flop 286 mayconsist of one-half a TTL dual flip-flop of the type 7476, while thedecade counter 284 may consist of a TTL decade counter type 7490. Theclock pulse KA is applied to the Ck terminal of the counter 284, and itis applied through an inverter 288 to the Ck terminal of the controlflip-flop 286. The output terminals of the counter 226 are connectedthrough a plurality of resistors 290 to the base terminals of aplurality of NPN transistors 292, which have their collectors connectedto the corresponding output terminals of the counters 284. The emittersof transistors 292 are connected in parallel to the J terminal offlip-flop 286, and they are also connected through an inverter 294 tothe P terminal of this flip-flop 286. The output signal at the Qterminal of the flip-flop 286 is applied through a diode 296 to decadecounter 224 through the circuitry operating through the inverter 262. Acomplement of this output signal is applied at the Q output terminal ofthe flip-flop 286 through a diode 298 and an inverter 300 to the Rstterminal of the counter 284.

A reset signal is applied to all counters, 220, 222, 224, 226 and 284,and all flip-flops, 216, 286, and 302 (described below), upon theinitial application of power to the machine. A slow charging capacitor304 is connected through resistor 306 to a positive voltage source fromwhich the power is supplied to the arithmetic logic unit 66 (FIG. 3).Capacitor 304 is coupled through resistors 308 and 310 to the baseterminals of a PNP transistor 312 and an NPN transistor 314,respectively. The emitter of transistor 312 is connected to the positivevoltage source, while the emitter of the transistor 314 is connected toground. A resistor 316 tied the collector of the transistor 312 to thebase of the transistor 314. A diode 318 applies this reset signalthrough an inverter 320 to a pair of parallel inverters 322 and 324where it is applied to the circuits that follow. From inverter 320, thisreset signal is also fed to an inverter 326 where it is applied to aplurality of diodes 328 connected to the respective reset terminals ofthe decade counters 220, 222, 224, 226, and 284 and the flip-flops 216,286, and 302.

The four output terminals of all five counters 220, 222, 224, 226, and284 are connected to a circuit for detecting a 0000 output, whichcircuit is comprised as follows: a plurality of diodes 330 connectingthe signal from the output terminals through resistor 332 to the base ofan NPN transistor 334, having its emitter connected to ground and itsbase connected through resistor 336 to ground.

This zero-detecting transistor 334 for both the decade counters 220 and222, connected in cascade, has the signal from its collector appliedthrough diode 338 to an inverter 340 which feeds the signal to a pair ofdiodes 342 and 344. The signal through diode 342 is applied to the resetterminal of the flip-flop 216, while the signal through diode 344 isapplied through inverter 238 through diode 346, inverter 348, and diode350 to the reset circuitry of the arithmetic logic unit 66, operatingthrough the inverter 320. The DD division signal is fed through theinverter 274 and diode 339 to this same circuitry operating throughinverter 340.

The signal from the collector of transistor 334 is also applied throughdiode 352 to the Cka lead of the dual flip-flop 302. The Cka lead of theflip-flop 302 also receives the input signal from C1 and C2, the twoleast significant binary coded digits in the operation signal. Signal C1is transmitted through an inverter 354 to a diode 356, while the C2signal is transmitted through a diode 358. When the information appliedat the Cka lead toggles the flip-flop 302, the output signal at theQ_(a) terminal is applied through a diode 360 directly to the resetcircuitry operating through the inverter 320 and described above.

The collector of transistor 334 for the decade counter 224 is connectedthrough diode 362 to an inverter 364 to a second diode 366, whichtransmits the signal to the Ckb lead of the flip-flop 302. As describedabove for the output at Q_(a) terminal of the flip-flop 302, an inputsignal at the Ckb lead that toggles an output signal at the Q_(b)terminal of the flip-flop 302 is fed through diode 368 to the resetcircuitry operating through the inverter 320. The signal from thecollector of the transistor 334 of this counter 224 is also appliedthrough a diode 370 through an inverter 372 to a pair of diodes 374 and376. The signal through diodes 374 is fed to the reset terminal of theflip-flop 216, while the signal through diodes 376 is fed through thecircuitry operating through the inverter 238 (described above).

The circuitry operating through the inverter 372 just described alsoreceives a signal through a diode 378 when the DD signal indicates adivision problem is present.

The signal from the collector transistor 334 for the next decade counter226, is fed through a pair of series connected inverters 380 and 382through diodes 384 to the reset circuitry, operating through theinverter 320. As in the description above, the presence of a DD signalfor a division problem is similarly fed through the circuit operatingthrough the inverter 380, since the DD signal is fed through theinverter 274 to a diode 386 connected to inverter 380. The signal fromthe collector of counter 226's transistor 334 is applied through a diode335 to the circuitry operated by flip-flop 216.

The final zero detection transistor 334 for the fifth counter 284 hasits collector connected through an inverter 387 to a diode 388 throughinverter 348 and diode 350 to the reset circuitry of the arithmeticlogic unit, operating through inverter 320. Again, in this case, thereset circuitry operating through inverter 348 also receives the DDsignal indicating division, which is transmitted through the inverter274 to a diode 390. Finally, a DD signal is also transmitted through adiode 392 to the Ckb terminal of flip-flop 302.

A selector switch 394 operates to select one of two binary coded inputsignals and places it on its output terminals to be transmitted to thedecade counter 224. The operation of selector switch 394 is controlledby the C1 operation mode signal, indicating by high level the selectionof either multiplication or division.

A second selector switch 396 is controlled by a DD signal indicatingdivision to route either the output signal from decade counter 224 orthe output signal from decade counter 222 to a set of four outputterminals containing the binary coded information signal for the leastsignificant digit of the answer, represented by the letter F.

When the clock pulses from flip-flop 216 have ceased, there is no longera signal at inverter 238, thus allowing timer 218 to time out from asignal through diode 398. The signal from diode 398 is received by thetimer 218 directly at its input terminals D and Th. It is connected tothe reset terminal through resistor 400. The timer 218 now has an outputsignal KQ at its output terminal indicating to the following circuitsthat a valid answer is now available.

If a valid answer has been selected, then input signal AA is transmittedthrough an inverter 402 and a diode 404 to an inverter 406, and theinput signal AB is transmitted through an inverter 408 through a diode410 to the inverter 406. Depressing clear switch 52, normally grounded,pulses a signal through diode 412 to the inverter 406 to step a problemlamp 38 in the holder 22, and to reset the circuits of the arithmeticlogic unit 66 through a diode 414 connected to the circuitry of theinverter 320.

In operation of the arithmetic logic unit 66, the application of powerinitially causes the slow charging capacitor 304, acting throughtransistors 312 and 314 to place a low level at the inverter 320 therebyoperating the reset lines of the machine through inverters 322, 324, and326. A plurality of diodes 328 apply the reset signal to the terminalsof the respective counters, 220-226, and flip-flops, 216, 286 and 302.

Arithmetic logic unit 66 begins to perform the problem present incounters 220, 222, 224 and 226 when the low level KR pulse from theinput storage unit 62 is received by the timer 200.

A two position selector switch 394 makes D output of unit 62's register146 available to counter 224 if an add or subtract problem has beenentered, or the B output of unit 62's register 142 if a divide ormultiply problem has been entered. The counter 220 has the A output ofunit 62's register 140 available, counter 222 -- B, and counter 226 --D. The operation mode selected was stored in the C register 144 of unit62. The corresponding C1 and C2 leads as well as the DD division signalhas preset the arithmetic logic unit 66 for operation.

A pulse from the timer 200 instructs the decoder 214 to route the datafrom the storage registers 140-146 of unit 62 through diodes 230, 232,and 234 to the appropriate counters 220, 222, 224, and 226 for theoperation selected. This same pulse also sets the flip-flop 216 toenable the successive adding or subtracting to take place in thecounters 220-226. Also the timer 218 is also set, but diode 398 preventsit from timing out until the counting has been completed. The fallingedge of the signal KQ of the timer 218 indicates to other circuits ofthe machine that the arithmetic logic unit 66 has completed the answerfor the problem.

The operation of the elements of arithmetic logic unit 66 can best beillustrated by considering some typical math problems for solution. Uponkeying the problem 3 + 4, the 3 is placed in the B register 142, theplus (+) in the C register 144, and the 4 in the D register 146 of theinput storage register unit 62 (FIG. 4). The load command from the timer200 through the decoder 214 loads the 3 into counter 222 and the 4 intocounter 224. The flip-flop 216 allows the clock pulse, KA to causedecade counter 222 to count upward, while at the same time counter 224is forced to count down. When counter 224 reaches zero, the transistor334 for counter 224 through inverter 372 forces the flip-flop 216 tostop the clock pulse KA to counter 224. Since decade counter 224 hasbeen clocked four times to reach zero, counter 222 has also receivedfour clock pulses, which in addition to the 3 preset in the counter 222causes it to now rest at 7. The lack of a signal at the output ofinverter 238 allows the timer 218 to time out, indicating through itsoutput signal KQ that a valid answer is now available.

In all operations except the division, the output of decade counter 222is the F signal from the selectors switch 396. In division, switch 396allows the decade counter 224 to provide the output signal F.

In subtraction the same process occurs as that described above foraddition, except counter 222 counts down instead of up. In order toprevent subtraction that results in negative answer, if counter 222reaches zero and steps back to 9, the flip-flop 302 will toggle causingthe signal at the QA terminal to operate the reset circuitry resettingthe machine through the invertor 320.

A divide by n counter is formed by the following components: counter226; counter 284; transistors 292; inverters 288, 294 and 300; and diode298. This means that the output signal at the Q terminal of flip-flop292 will only pulse once per each n, n being the value set in thecounter 226. This n counter is used in only multiplication and divisionto increment or decrement the counter 224 at a/nth of the angular clockpulse speed KA.

Arithmetic logic unit 62 multiplies and divides by a method calledserial decimal math, that is by successive addition and successivesubtraction, respectively. To illustrate the operation of these twoarithmetic operations, assume the problem 3 × 5 has been keyed into theinput storage register unit 62 (FIG. 4). The 3 is loaded into counter224 and the 5 into counter 226. Control flip-flop 216 is set so thatcounter 222 is clocked upward as counter 284 is clocked. When counter284 reaches 5, a pulse is applied to counter 224 to count it down,resetting counter 284. Counter 284 counts another five pulses and againpulses counter 224 down once more, resetting counter 284 again. Counter284 repeats counting five pulses and this time it forces counter 224 tozero, which is detected by its zero detector transistor 334, stoppingcontrol flip-flop 216. Counter 222 has seen 15 pulses during thissequence and has stopped at 5 since it can hold only 9. But, sincecounter 224 is cascaded to counter 220 which has registered a 1,indicating 10, the output of the two registers can be displayed throughoutput signals E and F as 15.

The operation for division is similar, but because of the importantdifferences this operation will also be illustrated by an example. Thedividend (which may be two places) is entered into counters 220 and 222,while the divisor is entered into counter 226. The clock pulse KAsubtracts the divisor in counter 226 from the dividend in counter 220and 222 until they register zero. Each time counter 284 is reset,counter 224 is counted up one place. When counters 220 and 222 equalszero, the zero detector transistor 334 for the counter 284 checks theposition of this counter 284, resetting the machine through thecircuitry of inverter 320 if the counter has not reached zero,indicating the problem was fractional. If counter 284 has reached zero,the answer is an integer and valid.

There are several special features of the arithmetic logic unit 66 todetect certain problems. If the multiplier to be loaded in decadecounter 226 is zero, the clock is not permitted to run and the answerwill always appear at zero. If zeros are entered into counter 226 for adivision problem, the inverters 380 and 382 will operate the resetcircuitry of the machine through inverter 320, as division by zero isnot permitted. The control flip-flop 302 with its output at terminal QBprevents counter 224 from exceeding 9 on division, since the machinemakes no provisions for an answer greater than 9. Thus the machine isreset if a problem such as 20 ÷ 2 is attempted.

The receipt of a problem and the selection of a correct answer enablesthe student to depress clear bar switch 52 to step the problem on theproblem sheet holder 22 and also reset the circuitry of arithmetic logicunit 66.

FIG. 8 illustrates a schematic diagram of the display multiplexers anddrivers 64 (FIG. 4) that selects the data outputs of all the registersand the counters in the machine, making them available for display.

A plurality of data selector switches 450, 452, 454 and 456 has seven oftheir eight input positions connected directly to storage registers orcounters in other circuits of the machine. These switches 450-456 mayconsist of the 74152 type TTL eight line to one line selectors. Thefourth position of each switch 450-456 is determined by one of the twooutputs of data selector 458. The eight input positions available to thedata selector 458 come from the 4 bit binary coded outputs of eitherstorage register 140 (FIG. 5) on the counter 220 (FIG. 6).

A plurality of diodes 460 detect the presence of the division mode andthrough inverter 462 operate the selector of the data selector switch458. The signal from the inverter 462 is applied to other circuits ofthe machine as the DD signal, setting up those circuits for the divisionoperation.

The C1 and C2 binary coded signals of the operation code are applied tothe input terminals of a decoder 464 to selectively operate a pluralityof format lamps 466 for the operations division, addition, subtractionand multiplication. The decoder 464 may comprise a 7442 type TTL BCD todecimal decoder.

A decoder and driver 468 has each of its four input terminals connectedto an output terminal W of one of the data selector switches 450-456.The seven output terminals, a-g, of the decoder and driver 468 areconnected through a plurality of resistors 470 to the 11 seven-segmentlight emitting diode displays of the machine. The decoder 468 maycomprise, e.g. 7447 type TTL seven-segment decoder driver.

A 16 position decoder 472 has three of its input terminals connected tothe three binary clock signals KA, KB, and KC. The fourth input terminalreceives the signal from the inverter 462, which indicates the selectionof the division mode. A plurality of diodes 474 connect selected outputterminals of the decoder and display 472 to the ZS and B1 controlterminals of the decoder and driver 468, thereby blanking it in certaindivide displays and suppressing zeros in 10 positions of two digitanswers. The decoder 472 may comprise, e.g., a 74154 type TTL four lineto 16 line decoder type.

In the operation of the display multiplexers and drivers unit 64 (FIG.4) the operation mode signal, C, is decoded by decoder and displayelement 464, thereby allowing the correct operation format lamps 466 tobe illuminated in the display window 46 of the keyboard encoder anddisplay 26 (FIG. 1).

A data selector switch 458 is conditioned by the division operationsignal to place the binary coded input from the E register of thearithmetic logic unit 66 (FIG. 3). In all other operation modes, thedata output from the A storage register 140 (FIG. 5) is made availableto the data selector switches 450-456.

The eight positions on the selector switches 450-456 are sequentiallymade available for display through the decoder and driver 468 by aseries of three clock pulses, KA, KB and KC. There are 11 digitaldisplays (DS1-DS111) in the keyboard encoder and display 26 (FIG. 1),five in the problem display window 46 and two each in the three windowssolution display 48.

FIG. 9 illustrates a schematic diagram for the random answer generatingunit 70 (FIG. 4), which takes the true answer of the problem as a basisto randomly generate two dissimilar numbers to be presented to thestudent as possible answers.

A free running oscillator 480 pulses the CK lead of a plurality of shiftregisters 482, 484, 486, and 488. The oscillator 480 may comprise, e.g.,an NE 555 IC type timer, while registers 482-488 may comprise 4 bit TTL74195 type shift registers. The oscillator 480 has its + and Rstterminals connected directly to a positive voltage source, while its Dinput terminal is connected through a resistor 481. Terminal D is alsoconnected to ground through a resistor 483 and a capacitor 485.Terminals Th and Tr of oscillator 480 are coupled through the capacitor485 to a common ground. Finally, the oscillator 480 has its FM terminalconnected through a capacitor 487 to ground, while its Gnd terminal isconnected directly to ground.

The KQ signal from the arithmetic logic unit 66, indicating the presenceof a valid answer, is connected through a capacitor 490 and a pull-upresistor 492, through a diode 494 to an inverter 496 connected to the Cklead of a shift register 498. The shift register 498 may comprise, forexample, a TTL 5 bit shift register type 7496. The register 498 is resetby the reset circuitry of the machine through a diode 500.

The shift register 498 is set up with a plurality of diodes 502connecting its output terminals through an inverter 504 to the DSterminal of the register 498, thereby functioning as a ring counter.

A decade counter 506 is pulsed by the binary clock signal KA toconstantly make its binary code decimal digit available to the inputs ofthe four registers 482-488. The counter 506 may comprise, e.g., a TTL7490 type decade counter. A plurality of diodes 508 enables the shiftregister 498 to cause data selectors 510 and 512 to successively connectoutputs of storage registers 482-488 to one side of a set of exclusiveOR gates 514. Data selectors 510 and 512 may comprise, e.g., two TTLdual 74153 type four line to one line selectors, while OR gates 514 maycomprise four TTL quad type exclusive OR gates.

A selector switch 516, controlled by the shift register 498, places theappropriate binary coded decimal digits of the answer at the other sideof the exclusive OR gates 514. Selector switch 516 may comprise, e.g., aTTL quad two line to one line type 74157 selector. A plurality of diodes517 takes the output of each of the exclusive OR gates 514 and appliesit through a resistor 518 to the base of an NPN transistor 520. Thetransistor 520 has its emitter connected to the ground, and its basegrounded through the resistor 522. The collector of the transistor 520is connected to a pull-up resistor 524 as well as to the Ck lead of theshift register 498 through inverter 526, a diode 528, an inverter 530, adiode 532, and the inverter 496. A flip-flop 540 is provided to applypulses at one-half the loading rate into registers 482-488 through diode542 to inverter 530. This causes the registers 482-488 to make at leasttwo changes before the exclusive OR gates 514 operate on a numberpresented at its input terminals.

The final position, Q4, of shift register 498 is coupled by a capacitor534 to an inverter 536, which also has its input connected to pull-up aresistor 538. The signal from inverter 536 is itself applied to aninverter 537 which has an output pulse KS, indicating that this circuithas completed the generation of the two "incorrect" random answers.

The random answer generator 70 (FIG. 4) operates to generate two randomanswers distinct from the correct answer generated by the arithmeticlogic unit 66 (FIG. 4). The free running oscillator 480 clocks the Cklead of each of the registers 482-488. The decade counter 506 isconstantly making the 10 binary coded decimal digits available forloading into these registers 482-488.

When the shift register 498 is pulsed to indicate a correct answer hasbeen generated, it enables the parallel load pin of the register 482 andcauses the selector switches 510 and 512 to make the output of thisregister 482 available to one side of the exclusive OR gates 514.Another selector switch 516 places the appropriate binary coded decimaldigit on the other terminal of the OR gate 514. If the two numbers arethe same, the transistor 520 and inverters 526 and 530 force the shiftregister 498 to keep trying new numbers until a difference is detected.As soon as this occurs, the shift register 498 advances to the nextposition, generating a number for the next register 484. This continuesuntil all registers 482-488 are filled, enabling the shift register 498to step to its last position, Q4, and apply a pulse to the capacitor 534and inverters 536 and 537 to indicate that the random answer generatingunit has completed its operation.

The machine reset circuitry resets the shift register 498 to the firstposition after each problem, so new answers may be generated upon thesignal that another valid answer has been generated by the arithmeticlogic unit 66 (FIG. 3). The outputs of the four registers 482-488 areused by the display multiplexer and drivers 64 (FIG. 4) as G, H, I and Jinputs.

FIG. 10 illustrates a schematic diagram of the answer position andselection control 72 (FIG. 4) which randomly selects which of threewindows in the solution display 48 (FIG. 1) is to display the correctanswer. In addition, this circuit operates to blank a window of display48 when an incorrect answer is selected, and it places the correctanswer in its proper position in the problem display 46 (FIG. 1).

Upon entry of a problem, computation of the correct answer, and randomgeneration of two incorrect answers, the KS information signal is fedthrough a plurality of diodes 548 to set the four flip-flops 550, 552,554, and 556. Each of the flip-flops 550-556 may comprise, e.g.,one-half a TTL dual 7476 type flip-flop. The pulse from the randomanswer generator unit 70 (FIG. 4) causes flip-flop 556 to generate asignal at its Q output terminal through a diode 558 to the Ck lead of ashift register 560. A 5 bit TTL 7496 type shift register may be used asthe register 560. The shift register 560 is clocked by the pulse KAthrough a diode 562. The signal from the two output terminals of theshift register 560 transmits in binary code a sequence of 1, 2 and 3 toset a three position selector switch 564. The output signals from thetwo terminals of the shift register 560 are fed through pins AA and ABto signal the arithmetic logic unit 66 (FIG. 4) of the status of theproblem being worked, and they also signal the display selector unit 68(FIG. 4) to determine the location of the correct and incorrect answersin the display window 48 (FIG. 1). A pair of diodes 566 take the outputsignal from the two terminals of the shift register 560 and feed themthrough an inverter 568 to the DS terminal of the register 560.

A plurality of diodes 570 apply the reset signal of the machine to thereset terminal of flip-flops 550-556. Momentary pushbuttons 50A, 50B,and 50C correspond to the three keys of the solution keyboard 50 of thekeyboard 26 (FIG. 1). A plurality of diodes 572 connect the pushbuttons50A, 50B and 50C to their corresponding reset terminals of flip-flops550, 552, and 554. Pushbuttons 50A, 50B and 50C are also connected tothe data selector switch 564. The presence of an output signal at the Yterminal of the selector 564 causes a signal, delayed by a pair ofcapacitors 574, to be routed through inverters 576 and 578 to aplurality of diodes 580 to the reset terminals of flip-flops 550, 552and 554. The signal from inverters 576 and 578 is also connecteddirectly to the reset terminal of the shift register 560, therebyresetting its two output terminals to 00.

The interrelationship of these components of the answer position andselection control unit 72 can be seen when considering how theyfunction. The three flip-flops 550, 552 and 554 control the operation ofthe solution display 48 (FIG. 1) through their respective output signalsplaced on pins BA, BB, and BC. The flip-flops 550-554 blank the solutiondisplay 48 while the machine is idle.

Upon the machine's generation of a correct answer and two randomlygenerated false answers, the KS signal causes flip-flop 556 to stop theshift register 560 at whatever number is generating when the signal isreceived. The binary coded output signal of the shift register 560,fixed by the action of the flip-flop 556, is taken from pins AA and ABto set the position of the correct answer in the solution display 48(FIG. 1). The same information from these two pins AA and AB, is used bythe arithmetic logic unit 66 (FIG. 3) to enable this unit to determinethe status of the problem.

A student's selection of an incorrect answer by depressing one of thebuttons 50A, 50B, or 50C causes the corresponding flip-flop 550-554 tobe reset, thereby blanking the corresponding solution display 48 (FIG.1). On the other hand, when the student selects the correct answer, theselector switch 564 causes all solution displays 48 to be blanked, andresets the shift register 560 to 00, thereby causing its output at pinsAA and AB to reflect that a correct answer has been selected and resetsthe answer position and selection control 72 to randomly position a nextcorrect answer. This enables the arithmetic logic unit 66 (FIG. 4) topermit the clear bar 52 to step the display board holder 22 (FIG. 1),while the correct answer is displayed in its appropriate place in theproblem display window 46 (FIG. 1).

FIG. 11 illustrates a schematic diagram of the display selector 68 (FIG.4) that selects which of the 11 seven segment light emitting diodedisplays shall be energized to display the information placed on thedisplay drive lines by the display multiplexer and driver units 64 (FIG.4).

The problem status signals AB and AA, the division operation signal DD,and the binary coded clock pulse KC are applied as four of the inputsignals to a set of four 16 position data decoders 600, 602, 604, and606. The two other binary coded clock signals of the machine, KA and KB,are the inputs to a fifth data decoder 608, having its four outputsapplied to the G1 and G2 terminals of the data decoder 600-606. Each ofthe data decoders 600-606 may comprise, e.g., a TTL four line to sixteenline 74154 type decoder.

The output terminals of the data decoders 600-606 are connected to aplurality of diodes 610 which are selectively connected to elevenseparate level shifting circuits through a plurality of inverters 612.Each of the eleven level shifting circuits has a current limitingresistor 614 connecting a positive voltage source to the output of theinverter 612, which is now applied through a resistor 616 and a diode618 to the base of an NPN transistor 620. The emitter of the NPNtransistor 620 is connected directly to ground, while its base isconnected through a resistor 622 to this ground. The signal from thecollector of the NPN transistor 620 is applied through a resistor 624 tothe base of a PNP transistor 626. The emitter of the transistor 626 isconnected to a positive voltage while the base of transistor 626 isconnected through a limiting resistor 628 to the same voltage source.Finally, the collector of each of the transistors 626 applies its signalto the anode of each of the eleven seven segment light emitting diodedigital displays. Additionally, a plurality of diodes 630 are providedto take the signal from the output terminals of the flip-flops 550, 552,and 554 (FIG. 9) and apply it to the base of the appropriate NPNtransistor 620 through the diode 618.

The interrelationship of these components of the display selector 68(FIG. 4) can now be seen when considering how they function. The inputlines AA, AB, and DD indicate the type and status of the problem beingworked, while the input lines KA, KB and KC are machine clock pulsescausing the display selector 68 to scan in sequence with the displaymultiplexer and driver 64 (FIG. 4). This information from these signalsis applied to the five data decoders 600-608, which operate togetherbasically as a 64 position switch. The output of this "switch" operatesthe eleven displays (DS1-DS11) for displaying the information thedisplay multiplexer and drivers 64 has placed on the other end of theeleven seven segment light emitting diodes. The anodes of each of theeleven displays (DS1-DS11) are energized by one of the level shiftersconsisting of an inverter 612, a resistor 614, a resistor 616, a diode618 and an NPN transistor 620, a resistor 622, a resistor 624, aresistor 628 and a PNP transistor 626.

The following logic table II indicates which of the eleven displays isenabled for each of the positions possible. The table II also lists theinformation the display multiplexer and driver 64 (FIG. 4) is passing onthe display lines.

                                      TABLE II                                    __________________________________________________________________________    Logic Table                                                                           DD 0  0  0  0  1  1  1  1                                                     AA 0  0  1  1  0  0  1  1                                                     AB 0  1  0  1  0  1  0  1                                             KA KB                                                                              KC                                                                       0  0 0     B-5                                                                              B-5                                                                              B-5                                                                              B-5                                                                              B-1                                                                              B-1                                                                              B-1                                                                              B-1                                           1  0 0     D-3                                                                              D-3                                                                              D-3                                                                              D-3                                                                              D-2                                                                              D-2                                                                              D-2                                                                              D-2                                           0  1 0     F-2                                                                              F-7                                                                              F-9                                                                              F11                                                                              F-5                                                                              F-7                                                                              F-9                                                                              F11                                           1  1 0     A-4                                                                              A-4                                                                              A-4                                                                              A-4                                                                              E-4                                                                              E-6                                                                              E-8                                                                              E10                                           0  0 1     G  G  G  G  G  G-8                                                                              G-6                                                                              G-6                                           1  0 1     H  H-9                                                                              H-7                                                                              H-7                                                                              H  H-9                                                                              H-7                                                                              H-7                                           0  1 1     I  I  I  I  I  I10                                                                              I10                                                                              I-8                                           1  1 1     J  J11                                                                              J11                                                                              J-9                                                                              J  J11                                                                              J11                                                                              J-9                                           __________________________________________________________________________     Letters indicate registers selected by the display multiplexers.               Numbers indicate displays selected by the display selector.             

FIG. 12 illustrates a schematic diagram for the problem display holder22 (FIG. 1) which has a plurality of problem lamps 38 to light the nextproblem on sheet 32 as the student correctly answers problems.

A positive voltage source is connected through a resistor 650 to a diode652 connected to a ground point by a capacitor 654. Upon initialapplication of power, the diode 652 forces a latch, formed by inverters656 and 658 connected by diodes 660 and 662, into a "standby" mode. Inthe standby mode, the output of inverter 656 presets a low level in the10 bit column register consisting of shift registers 664 and 666, whileit also presets a low level in the ten bit row register consisting ofshift registers 668 and 670. The shift register 664-670 may consist,e.g., of four TTL 5 bit shift registers type 7496.

The output of inverter 656 is also applied through a resistor 672 to thebase of a PNP transistor 674, which has its emitter connected to apositive voltage source while its base is biased by this voltage throughresistor 676. The output of the collector of the transistor 674 isconnected to ground through a diode 678 in parallel with a solenoid coil680.

The locking switch 34 connects a positive voltage source to a groundedcapacitor 682 through a resistor 684, which is also connected through adiode 686 to the latch circuitry operating through the inverter 658.

A step input pulse is received from the arithmetic logic unit 66 (FIG.3) through inverter 688 to the clock leads of the column shift registers664 and 666. The row shift registers 668 and 670 in turn are clocked bythe last output stage of the shift register 666.

The 10 output terminals of the column shift registers 664 and 666 areindividually connected through a plurality of resistors to the base of aplurality of PNP transistors 692. The transistors 692 have theiremitters connected to a positive voltage source while their baseterminals are biased by this voltage source through a plurality ofresistors 694. The output of the collector of the transistor 692 enablesone terminal of a plurality of problem lamps 38 through a plurality ofdiodes 696.

A plurality of diodes 698 connect the first nine output terminals of thecolumn shift registers 664 and 666 to an inverter 700 that has itsoutput connected to the DS terminal of the first column shift register664. The 10th output terminal of the two column shift registers 664 and666 (the Q5 terminal of the shift register 666) is connected to theclock leads of the two interconnected row shift registers 668 and 670.The 10 output terminals of the two interconnected row shift registers668 and 670 are connected to a plurality of PNP transistors 700, whichhave each of their base terminals connected through a plurality ofresistors 702 to a positive voltage source, while the collectors areconnected to a common ground. The emitter of each of the transistors 700enables the other terminal in a row of problem lamps 38.

The last output terminal, Q5, of the column shift register 666, and thelast terminal, Q5, of the row shift register 670 are connected throughdiodes 704 and 706, respectively, which are connected to a resistor 708to the base of an NPN transistor 710. The emitter of the transistor 710is connected to a ground, while the collector is connected to a positivevoltage source through a resistor 712, and the collector is alsoconnected through capacitor 714 and resistor 716 to the same voltagesource. Finally, the diodes 718 connect the capacitor 714 to the latchcircuitry, operating through the input to the inverter 656.

The circuit components for the problem display holder 22 can now beconsidered as they operate as part of the electronic mathematicstraining machine. The initial application of power causes the latch,consisting of inverters 656 and 658 with their outputs tied to the inputof the other through the diodes 660 and 662, to be set in the standbymode. This standby mode jams the column and row registers 664-670,causing them to ignore step signals from the arithmetic logic unit 66,while at the same time placing the locking pin 36 in an unlockedposition through the solenoid coil 680.

When the student slides a problem sheet 32 into place, the lockingswitch 34 now sets the latch, described above, in the "lock" mode. Inthis mode, the output of the inverter 656 causes the solenoid coil 680to activate the locking pin 36, preventing the removal of the problemsheet 32 until both the column and row shift registers 664-670 have beenstepped through all problems on the sheet 32. Further, the lock modecauses the output of inverter 656 to remove the preset (jam) signal fromall registers, allowing them to advance one position when receiving astep input from the arithmetic logic unit (FIG. 3) through the output ofinverter 688.

Each time the input to inverter 688 goes low, a clock pulse is appliedto the column shift register 664 and 666, thereby advancing the lowlevel one position. The advance of this low level allows the transistor692 to successively conduct, selecting another problem lamp 38 forillumination. The plurality of diodes 696 holds the input of inverter700 low during the first nine steps, but on the ninth step the inverter700 is no longer held low, allowing its output to go low. On the nextsucceeding step, the tenth step, a low level is loaded into the columnshift register 664 through its terminal DS to replace the one shiftedout of the last output terminal, Q5, of the register 666. This circuitarrangement continuously shifts a single low level through the 10 outputstages of the column shift register 664-666.

The last output of the column shift registers 664-666 is fed to theclock leads of the row registers 668 and 670. On the final 10th step,this output lead of the register 666 goes high to cause the row register668-670 to select another group of 10 lamps.

At the end of ninety-nine steps, the last stage output from both thecolumn shift register 666 and the row shift register 670 go low, therebyallowing the AND gate formed by diodes 704 and 706, resistor 708, andthe transistor 710 to go high. This high level signal at the collectorof the transistor 710 allows the capacitor 714 to have a zero net chargeby the action of resistor 712 and 716. Thus, upon the 100th (and last)step, the AND gate (described above) again goes low, now forcing thecapacitor 714 through the diode 718 to reset the latch, described above,in the standby mode. As stated previously, when the circuitry of theproblem display holder 22 is in this mode the registers 664-670 arepreset and the locking pin 36 releases so the problem sheet 32 may nowbe removed.

FIG. 13 illustrates a schematic diagram for the random problem controlunit 74 (FIG. 4) which can be inserted into the circuitry of theelectronic mathematics trainer for randomly generating arithmeticproblems and entering these problems automatically into the inputstorage unit 62 (FIG. 4).

A shift register 720 receives its input from the cyclic number output ofthe decade counter 506 (FIG. 9) of the random answer generator. Theregister 720 is clocked through its CK terminal by the free-runningoscillator 480 (FIG. 9). The binary coded information from the fouroutput terminals of shift register 720 is applied through a plurality ofdiodes 722 to a plurality of inverters 724 that are connected to theinput storage register unit 62 (FIG. 4). The output signal from thefirst two output terminals, Q_(a) and Q_(b), of register 720 areconnected through a plurality of inverters 726, a plurality of diodes728 and a second set of inverters 730 before passing through diodes 722.

The output of the free-running oscillator 480 (FIG. 9) is also connectedthrough capacitor 732, grounded by resistor 734, through an inverter 736to the K signal lead going to the input storage registers and controlunit 62 (FIG. 3).

A control flip-flop 738 is set through its P_(a) terminal by the resetinverters 324 (FIG. 7). The output signal from the Q_(a) terminal offlip-flop 738 is applied through the D_(s) terminal of control shiftregister 740, thereby allowing a low level to be shifted into the firstposition of register 740. The register 740 is clocked through its Ckterminal by the free-running oscillator 480 (FIG. 9). As soon as the lowis shifted into register 740, the plurality of diodes 742 attached tothe four output terminals of register 740 force inverter 744 high,thereby allowing a plurality of diodes 746 to open inverter 736 and theplurality of inverters 724. This allows the random members to be clockedinto the keyboard input lines 1, 2, 4, and 8 shown in the input storageregisters 140-146 (FIG. 6). A plurality of diodes 742 also resetflip-flop 738 through its terminal C1_(a), allowing only one set of fourinputs to be generated. Manually closing the automatic problem switch 54disables the random problem control unit 74, and allows problems to bemanually keyed into the mathematics trainer.

The third output terminal, Q_(c) of the register 740 is connectedthrough a manually controlled five position operation selector switch 56to generate the operation code for the randomly generated problem.Operation selector switch 56a is connected through a diode 746 to theoutput from the Q_(a) terminal of register 720 at a point between diode728 and inverter 730. Operation selector switch 56b is connected througha diode 748 to the output of the Q_(b) terminal of register 720 at apoint between diode 728 and the inverter 730. Operation selector switch56c is connected through a diode 750 to an input from the Q_(a) terminalof register 720 at a point after diode 722. Operation selector switch56d is connected through a diode 742 to the output from the Q_(b)terminal of register 720 at a point after its diode 722. Finally, arandom selection of the arithmetic operation is achievable when switches56a-56d are in the off position, and the output of Q_(c) of the register740 is connected directly through the plurality of diodes 754 to theoutput from the Q_(c) and Q_(d) terminal of register 720 at a pointafter diodes 722.

Operation of switches 56a and 56b will cause a logic low signal to beloaded during the third digit generation, irregardless of the data ofthe output signal from terminal Q_(a) and Q_(b) of register 720.Likewise, operation of switches 56c and 56d will cause a logic highsignal to be loaded into the keyboard line irregardless of the state ofthe outset signal from terminal Q_(a) and Q_(b) of register 720.Different combinations of the switch 56 will allow a desired arithmeticoperation to be jammed into the machine, or allow a random operation tobe entered.

The electronic mathematics trainer described hereinabove serves toencourage students and the like in developing their arithmetic skills. Astudent is free to selectively enter any valid arithmetic problems,since the trainer will accept only integer operations and positivesigned numbers. The entry of an invalid problem will cause the trainerto reset, making it ready for a valid problem.

The problems are selected from the problem sheet bearing a plurality ofarithmetic problems.

The machine rewards the student at the outset by displaying a correctlyentered problem to give him a feeling of achievement in approaching theproblem. In addition, showing the problem to the student in the displayserves another purpose in repeating the problem to the student. At thispoint, the student has seen the arithmetic problem first from a problemsheet, he has taken some action to key this same problem into thetrainer, and he sees the problem for the third time as it is displayedon the trainer.

The next action the student will take is to select the correct answerfor the entered problem from a solution display that includes thecorrect answer and at least one incorrect answer. The trainer randomlypositions the correct answer in the solution display to prevent thecorrect answer from appearing in the same position during the solutionof a number of problems. The trainer provides an incentive to thestudent in selecting the correct displayed answer by enabling him torapidly progress through a number of arithmetic problems in a givenexercise.

The student is alerted to the selection of an incorrect answer by theblanking or elimination of that answer from the solution display.However, the problem remains unsolved and the student must find thecorrect answer to the problem before the trainer can be cleared forentry of a next arithmetic problem. This trainer enables each student towork at his own pace, so that slow learners are not embarrassed byholding back other students in the class and fast learners may advanceat the rate they set forth themselves. When the student selects thecorrect answer, the solution is reinforced in the student's mind bydisplaying it adjacent to the problem. The student may now clear theproblem and solution display area of the machine making it ready for theentry of a next problem.

The next problem to be entered by the student will be the nextilluminated problem on the problem sheet of the trainer. A teacher maythus visually check the progress of each student in a particularexercise by glancing at the problem sheet holder.

Whereas the present invention has been described with respect tospecific embodiments thereof, it will be understood that various changesand modifications will be suggested to one skilled in the art, and it isintended to encompass such changes and modifications as fall within thescope of the appended claims.

What is claimed is:
 1. An electronic mathematics trainercomprising:means for selectively entering an arithmetic problem to besolved, means for computing the correct answer to the arithmeticproblem, means for generating at least one incorrect answer to thearithmetic problem, means for displaying the correct and incorrectanswers, means for randomly positioning the correct and incorrectanswers on said display means, means operable for selecting one of thedisplayed answers, and means for clearing the entered arithmetic problemupon the selection of the correct displayed answer.
 2. The electronicmathematics trainer of claim 1 and further comprising:a problem displaywherein the unsolved entered arithmetic problem is displayed.
 3. Theelectronic mathematics trainer of claim 2 and further comprising:meansfor retaining the display of the entered problem in said problem displayuntil the selection of the correct displayed answer.
 4. The electronicmathematics trainer of claim 2 and further comprising:means for enteringthe selected correct displayed answer in said problem display adjacentthe displayed unsolved entered arithmetic problem.
 5. The electronicsmathematics trainer of claim 2 wherein said means for displaying answersand said problem display comprise a plurality of light emitting diodes.6. The electronic mathematics trainer of claim 2 wherein said means fordisplaying answers and said problem display comprise a plurality of heatemitting elements.
 7. The electronic mathematics trainer of claim 1wherein said means for selectively entering an arithmetic problem to besolved includes a keyboard containing keys for the decimal numbers zerothrough nine and the four arithmetic operation modes of addition,subtraction, multiplication, and division.
 8. The electronic mathematicstrainer of claim 7 and further comprising:means for retaining theoperation mode of the entered arithmetic problem after clearing theentered arithmetic problem upon the selection of the correct displayedanswer.
 9. The electronic mathematics trainer of claim 7 and furthercomprising:means for preventing the entering of more than one operationmode for an arithmetic problem.
 10. The electronic mathematics trainerof claim 7 wherein said keyboard includes keys embossed with Braillealphabet characters or similar characters for indicating the function ofsaid key to a sightless person.
 11. The electronic mathematics trainerof claim 1 and further comprising:means for indicating whether theselected displayed answer is the correct answer or an incorrect answer.12. The electronic mathematics trainer of claim 1 and furthercomprising:a problem list bearing a plurality of arithmetic problems, aproblem list holder for receiving said problem list, means in saidholder for sequentially indicating ones of the arithmetic problems to beselectively entered and solved, and means in said display holderresponsive to the selection of the correct displayed answer foradvancing said indicting means to a next arithmetic problem.
 13. Theelectronic mathematics trainer of claim 1 and further comprising:meansfor accepting only valid arithmetic problems to be solved by saidcomputing means, wherein said valid problems include only integeroperations and positive signed numbers.
 14. An electronic mathematicstrainer comprising:means for selectively entering an arithmetic problemto be solved, a problem display for indicating the entered arithmeticproblem, means for computing the correct answer to the enteredarithmetic problem, means for generating at least one incorrect answerto the entered arithmetic problem, a solution display for indicating thecorrect and incorrect answers, means for randomly positioning thecorrect and incorrect answers in said solution display, means operablefor selecting one of the displayed answers, means for indicating theselection of a correct displayed answer, means for indicating theselection of an incorrect displayed answer, and means for clearing theentered arithmetic problem upon selection of the correct displayedanswer.
 15. The electronic mathematics trainer of claim 14 and furthercomprising:means for accepting only valid arithmetic problems to besolved by said computing means, wherein said valid problems include onlyinteger operations and positive signed numbers.
 16. The electronicmathematics trainer of claim 14 and further comprising:means fordisplaying the selected correct displayed answer in the proper place inthe format of the displayed problem.
 17. The electronic mathematicstrainer of claim 14 and further comprising:means for retaining theoperation mode of an entered arithmetic problem upon selection of thecorrect displayed answer and subsequent to operation of said clearingmeans to clear the entered arithmetic problem.
 18. The electronicmathematics trainer of claim 14 wherein said means for selecting one ofthe displayed answers includes a plurality of answer selection keyslocated so that each of said keys is adjacent a displayed answer in saidsolution display.
 19. The electronic mathematics trainer of claim 14wherein said solution display and said problem display include aplurality of light emitting diodes.
 20. The electronic mathematicstrainer of claim 14 wherein said solution display and said problemdisplay include a plurality of heat emitting elements.
 21. Theelectronic mathematics trainer of claim 14 wherein said means forselectively entering an arithmetic problem includes a keyboardcontaining keys for the decimal numbers zero through nine and the fourarithmetic operations of addition, subtraction, multiplication, anddivision.
 22. The electronic mathematics trainer of claim 21 whereinsaid keyboard includes keys with raised characters of the Braillealphabet or similar characters for indicating the function of saidkeyboard to a sightless person.
 23. The electronic mathematics trainerof claim 14 wherein said means for indicating the selection of anincorrect displayed answer include means for blanking said solutiondisplay of the incorrect answer.
 24. An electronic mathematics trainercomprising:a problem sheet bearing a plurality of arithmetic problems,an arithmetic problem display holder for receiving said problem sheet,means in said display holder for sequentially indicating ones of thearithmetic problems on said problem sheet to be solved, a keyboardencoder for entering the arithmetic problem indicated on said displayholder, a display unit for displaying the arithmethic problem entered insaid encoder, means for computing a correct answer to the arithmeticproblem entered by said keyboard encoder, means for generating at leastone incorrect answer to the arithmetic problem entered by said keyboardencoder, means on said display unit for randomly displaying the correctand incorrect answer, means operable for selecting one of the displayedanswers, means in said display holder responsive to the selection of thecorrect displayed answer for advancing said indicating means to a nextarithmetic problem on said problem sheet, and means for clearing thearithmetic problem displayed by said display unit upon selection of thecorrect displayed answer.
 25. The electronic mathematics trainer ofclaim 24 wherein said display unit includes means for entering thecorrect answer in the display of the arithmetic problem upon selectionof the correct displayed answer.
 26. The electronic mathematics trainerof claim 24 and further comprising:means for retaining the arithmeticoperation of an entered arithmetic problem after said means for clearingthe arithmetic problem clears the arithmetic problem.
 27. The electronicmathematics trainer of claim 24 and further comprising:means forindicating the selection of the correct displayed answer.
 28. Theelectronic mathematics trainer of claim 24 and further comprising:meansfor indicating the selection of an incorrect displayed answer.
 29. Theelectronic mathematics trainer of claim 24 and further comprising:meansin said display holder for retaining said problem sheet until theselection of the correct displayed answer for all the problems on saidproblem sheet.
 30. The electronic mathematics trainer of claim 24wherein said display unit comprises a plurality of light-emittingdiodes.
 31. The electronic mathematics trainer of claim 24 wherein saiddisplay unit comprises a plurality of heat emitting elements.
 32. Theelectronic mathematics trainer of claim 24 wherein said keyboard encodercomprises keys containing raised Braille alphabet characters or similarmeans for indicating the functions of said keys to a sightless person.33. An electronic mathematics trainer comprising:a problem sheet bearinga plurality of arithmetic problems to be entered into said keyboardencoder, a problem sheet holder for receiving said problem sheet, meansin said holder for sequentially indicating an arithmetic problem on saidproblem sheet, a student operated keyboard encoder for selectivelyentering the decimal numbers and arithmetic operation mode of anarithmetic problem on said problem sheet to be solved, a problem displayfrom displaying the entered arithmetic problem, means for computing thecorrect answer, means for generating at least one incorrect answer, asolution display for displaying the correct and incorrect answers, meansfor randomly positioning the correct and incorrect answers in saidsolution display, means operable for selecting one of the displayedanswers, means for indicating the selection of a correct answer, meansfor indicating the selection of an incorrect answer, means fordisplaying the selected correct answer on said problem display, means insaid holder responsive to the selection of the correct displayed answerfor advancing said indicating means to a next problem, means forretaining said problem sheet in said holder until the correct displayedanswer has been selected for all problems on said problem sheet, andmeans operable for clearing the arithmetic problem entered by saidkeyboard encoder upon selection of the correct displayed answer.
 34. Theelectronic mathematics trainer of claim 33 and further comprising:meansfor accepting only valid arithmetic problems for said computing means,wherein said valid problems include only integer operations and positivesigned numbers.
 35. The electronic mathematics trainer of claim 33wherein said solution display includes means for simultaneouslydisplaying the correct and incorrect answers.
 36. The electronicmathematics trainer of claim 33 and further comprising:a plurality ofmomentary pushbuttons with one of said pushbuttons adjacent each of thedisplayed answers to provide said means for indicating the selection ofthe correct or an incorrect answer.
 37. The electronic mathematicstrainer of claim 33 and further comprising:means for retaining theentered arithmetic operation mode upon operating the means for clearingthe arithmetic problem entered by said keyboard encoder.
 38. Theelectronic mathematics trainer of claim 33 and further comprising meansfor correcting an erroneous entry of a decimal number or an arithmeticoperation of an arithmetic problem.
 39. The electronic mathematicstrainer of claim 33 wherein said keyboard encoder includes means for asightless person to enter the decimal numbers and arithmetic operationmode of an arithmetic problem to be solved, wherein said solutiondisplay includes means for enabling a sightless person to detect thedisplay of correct and incorrect answers, wherein said problem anddisplay includes means for enabling a sightless person to determine theentered arithmetic problem, and wherein said means for indicating theselection of a correct or an incorrect answer includes means forenabling a sightless person to determine whether the selected answer iscorrect or incorrect.
 40. A method of teaching arithmetic skills,comprising the steps of:displaying a plurality of arithmetic problems tobe solved, entering the decimal numbers and the arithmetic operationmode of one of the arithmetic problems into an electronic mathematicstrainer, displaying the entered arithmetic problem without an answer tothe student, computing a correct answer and at least one incorrectanswer, randomly displaying the correct answer and at least oneincorrect answer, selecting one of said answers, and displaying thecorrect answer together with the entered problem upon the selection of acorrect answer.
 41. The method of teaching arithmetic skills of claim 40and further comprising the step of:indicating to a student when anincorrect answer is selected.
 42. The method of teaching arithmeticskills of claim 40 and further comprising the step of:indicating to astudent when a correct answer is selected.
 43. The method of teachingarithmetic skills of claim 40 and further comprising the stepof:identifying in sequence one of the plurality of displayed arithmeticproblems upon each selection of a correct displayed answer for enteringinto the electronic mathematics trainer for solution.
 44. The method ofteaching arithmetic skills of claim 43 and further comprising the stepof:retaining the display of a plurality of arithmetic problems for usein the electronic mathematics trainer until a correct displayed answerhas been selected for all the displayed arithmetic problems.
 45. In amathematics training system, the combination comprising:means forselectively entering an arithmetic problem to be solved, means forcomputing the correct answer for the problem to be solved, means forcomputing at least one incorrect answer for the problem to be solved, ananswer display having at least two display positions, and means forrandomly controlling the display of said correct and incorrect answerson said answer display, such that said correct answer may be displayedon any of said display positions.
 46. The combination of claim 45wherein two incorrect answers are generated and further comprising:threedisplay positions in said answer display.
 47. The combination of claim45 and further comprising:a plurality of two position electronicswitches for controlling the operation of said display positions. apulsed shift register for continuously outputting a sequence of digitalsignals each corresponding to a distinct display position fordetermining the location of said correct answer, a position selectorswitch for receiving the continuous output of digital signals from saidshift register and for controlling the output of said electronicswitches, and a data control switch for randomly stopping said shiftregister, the output of said register determining the location of saidcorrect answer in said display positions.
 48. The combination of claim45 and further comprising:a plurality of switches corresponding to eachof the data display positions for selecting an answer, and means forblanking the display position displaying an incorrect answer upon itsselection.
 49. The combination of claim 46 wherein said two positionselectronic switches comprise multivibrators.
 50. The combination ofclaim 46 and further comprising:a problem display for formatting anarithmetic problem, means for generating digital clock signals, aplurality of data selectors composing an electronic switch continuouslyrotated through all of the switch positions by said digital clocksignals, thereby enabling the problem to be solved to said problemdisplay and the correct and incorrect answers to be displayed in saidanswer display, means for detecting the operation mode of the trainingsystem, and at least one operation selector switch responsive to saiddetecting means for selectively routing the problem to be solved on thecorrect answer to said data selectors.
 51. The combination of claim 45and further comprising:means for suppressing the display of leadingzeros in answers displayed by said answer display.
 52. The combinationof claim 45 wherein said means for computing in incorrect answercomprises:a free running oscillator, a plurality of incorrect answershift registers clocked by said oscillator, means for generating digitalclock signals, a decade counter pulsed by said digital clock signals, acontrol shift register responsive to the computation of a correct answerby the trainer, a ring counter operated by said control shifter forenabling successive ones of said incorrect answer shift registers toload data from said decade counter, a plurality of exclusive OR gates, aplurality of data selectors for loading the output from said incorrectanswer shift registers to one side of said OR gate upon said dataselectors being enabled by said ring counter, a correct answer selectorfor loading the correct answer on the other side of said OR gate, meansfor loading a next number into the enabled one of said incorrect answershift registers from said decade counter upon said OR gates indicatingthe correct answer and the output of said incorrect answer shiftregister are the same, and means for advancing said control shiftregister to the next one of said incorrect answer shift registers uponsaid OR gate detecting that the correct answer differs from the outputof the enabled one of said incorrect answer shift registers.
 53. Theelectronic circuit of claim 52 and further comprising:a two positionelectronic control switch for applying a clock pulse to the plurality ofsaid incorrect answer shift registers upon said OR gates first detectinga difference between the output of said incorrect answer shift registersand the correct answer.
 54. In a mathematics training system, thecombination comprising:means for selectively entering an arithmeticproblem to be solved, means for computing the correct answer for aproblem to be solved, means for randomly generating a sequence ofnumbers, means for comparing the correct answer to the randomlygenerated numbers, means for selecting a randomly generated numberdetermined by said comparing means to be different from the correctanswer, and means for displaying the correct answer and a randomlygenerated number determined by said selecting means.
 55. The combinationof claim 54 wherein said selecting means operates only upon the secondnumber determined by said comparing means to be different from thecorrect answer, thereby preventing the same randomly generating numbersfrom being repeatedly selected.
 56. An electronic mathematics trainercomprising:means for automatically generating a random arithmeticproblem; means for automatically entering the randomly generatedarithmetic problem, a display unit for displaying the arithmetic problemautomatically entered, means for computing a correct answer to theautomatically entered arithmetic problem, means for generating at leastone incorrect answer to the automatically entered arithmetic problem,means on said display unit for randomly displaying the correct andincorrect answer, means operable for selecting one of the displayedanswers, and means for clearing the arithmetic problem displayed by saiddisplay unit on selection of the correct displayed answer.
 57. Theelectronic mathematics trainer of claim 56 wherein said display unitincludes means for entering the correct answer in the display of thearithmetic problem upon selection of the correct displayed answer. 58.The electronic mathematics trainer of claim 56 and further comprising:means for indicating the selection of the correct displayed answer. 59.The electronic mathematics trainer of claim 56 and further comprising:means for indicating the selection of an incorrect displayed answer. 60.The electronic mathematics trainer of claim 56 and further comprising:means for selecting the arithmetic operation for the automaticallygenerated random arithmetic problem.
 61. The electronic mathematicstrainer of claim 56 and further comprising: means for selecting randomgeneration of the operation mode of the automatically randomly generatedarithmetic problem.
 62. A method of teaching arithmetic skills,comprising the steps of:automatically generating a random arithmeticproblem to be solved, automatically entering the decimal numbers andarithmetic operation mode of the generated arithmetic problem into anelectronic mathematics trainer, displaying the entered arithmeticproblem without an answer to the student, computing a correct answer andat least one incorrect answer, randomly displaying the correct answerand at least one incorrect answer, selecting one of said answers, anddisplaying the correct answer with the entered problem upon theselection of a correct answer.
 63. The method of teaching arithmeticskills of claim 62 and further comprising the step of: indicating to astudent when an incorrect answer is selected.
 64. The method of teachingarithmetic skills of claim 62 and further comprising the step of:indicating to a student when a correct answer is selected.